Abstract

Reconfigurable computing and board level integration have experienced phenomenal advancement in the last decade. These have enabled the functionality for radar system control, signal processing and data acquisition to be migrated from rack-sized systems and extensive custom circuitry onto off-the... Show moreReconfigurable computing and board level integration have experienced phenomenal advancement in the last decade. These have enabled the functionality for radar system control, signal processing and data acquisition to be migrated from rack-sized systems and extensive custom circuitry onto off-the-shelf cards hosted in generic computer workstations. The Software-Defined Digital Down Converter (SD3C) is a complete radar processor built on a single commercial digital transceiver card. The off-the-shelf card is based on a Field Programmable Gate Array (FPGA). Multi-channel IF digitization, down-conversion, transmit pulse generation, and digital timing signals are all provided by the PMC format card. The hardware vendor supplies core firmware for controlling the hardware assets on the card and integrating with the host operating system, and the developer simply inserts application specific processing blocks within this framework. Flexible firmware and host software implement a variety of signal processing tasks, such as configurable filtering, data tagging, pulse coding/decoding, and coherent integration. Other capabilities are possible. Reconfiguring the signal processing behavior is achieved simply by loading different firmware. A single card supports up to four channels of down conversion and one transmit pulse output. Multiple cards can be combined to increase the number of channels in the system. The SD3C system requirements and design are presented, with application to a newly developed spaced antenna wind profiler. The functional components and their interconnections are explored, with discussion of the development challenges and lessons learned. Robust and well-designed software is the key to easily deploying the processor in different profilers, and the SD3C host software architecture is detailed. Performance measures and observational results are given for the NCAR 449 MHz wind profiler. Show less